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Incorporating Monitors in Reactive Synthesis without Paying the Price
(19th International Symposium on Automated Technology for Verification and Analysis, 2021)
Temporal synthesis attempts to construct reactive programs
that satisfy a given declarative (LTL) formula. Practitioners have found
it challenging to work exclusively with declarative speci cations, and
have found ...
Runtime Verification meets Controller Synthesis
(2022)
Reactive synthesis guarantees correct-by-construction controllers from logical specifications, but is costly—2EXPTIME-complete in the size of the specification. In a practical setting, the desired controllers need to ...
ppLTLTT : Temporal Testing for Pure-Past Linear Temporal Logic Formulae
(2023)
This paper presents ppLTLTT, a tool for translating pure-past linear temporal logic formulae into temporal testers in the form of automata. We show how ppLTLTT can be used to easily extend existing LTL-based tools, such ...